About Careertakes

👉 Important disclosure: Careertakes is a third-party recruiting platform supporting this hiring process. If selected, you will be employed directly by our client, IT.

Applicants for this role may also receive access to additional matched opportunities through the Careertakes platform.

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Role overview

Confidential Client is seeking an early-career ASIC Engineer I to join its custom silicon team in International, WA. In this hands-on role you'll contribute to chip development across RTL design, verification, physical design support, and SoC integration. You'll work with cross-functional engineers to take features from specification to silicon while learning industry-standard flows and tools.

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What You’ll Do

• Design and implement RTL for digital logic blocks using Verilog/SystemVerilog (or VHDL where applicable)
• Build and run verification environments to validate design functionality and coverage
• Support synthesis, timing analysis, and physical design flows (place-and-route, timing closure)
• Debug design issues via simulation, waveform analysis, and root-cause investigation
• Collaborate with architecture, verification, physical design, and software teams to move features from spec to silicon
• Document design decisions and present progress and tradeoffs to your team

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Basic qualifications

• Bachelor’s or Master’s degree program in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a final graduation date of May 2027 or earlier
• Coursework or project experience in digital logic design and computer architecture
• Familiarity with a hardware description language (Verilog, SystemVerilog, or VHDL)
• Understanding of core digital design concepts: combinational and sequential logic, finite state machines, timing, and clocking

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Preferred qualifications

• Degree focus or coursework in VLSI, digital design, or computer architecture
• Experience with industry-standard EDA tools (Cadence, Synopsys, or equivalent)
• Scripting experience for automation and design flows (Python, Perl, TCL, shell)
• Prior internship, research, or lab experience in chip design, embedded systems, or hardware development
• Strong debugging skills and the ability to communicate technical tradeoffs clearly

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Location & worksite

• Worksite: International, WA, US (on-site or as specified by Confidential Client for this role)
• This listing is for the International, WA location (postal code 98194). Confirm exact worksite and schedule during the interview process.

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Compensation & benefits

• Estimated national benchmark (for similar roles): $147,559 per year (estimated)
• Starting pay listed for Seattle / WA area in source materials: $116,100 USD annually
• Additional benefits: typical early-career benefits such as health and wellness programs, retirement/401(k) matching, and professional development opportunities — details provided by Confidential Client during recruiting

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Application & interview notes

• You will be considered based on your academic record, project and lab experience, and demonstrated knowledge of RTL and verification concepts.
• Interviews will evaluate hands-on skills, problem solving, and ability to communicate design tradeoffs.
• Careertakes may surface additional matched roles to qualified applicants through its platform.

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Legal & accommodations

Careertakes and Confidential Client are committed to providing equal employment opportunity. If you need a workplace accommodation during the application or hiring process, please notify the recruiting contact and we will work with you to provide reasonable support.

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Equal Opportunity & Hiring Transparency

Careertakes and our client are Equal Opportunity Employers committed to building a diverse and inclusive workforce. We prohibit discrimination or harassment of any kind. To support a fair and efficient hiring process, AI tools may be used to assist with application review or resume screening. These tools do not replace human decision-making. Final hiring decisions are made by people.

If you have questions about how your data is used, please contact us directly.